TSMC is preparing for the 3-nanometer production process: during its annual Technology Symposium, the Taiwanese foundry explained the salient features of the new system, and also illustrated what the evolutions of the 5-nanometer one will be – whose first SoCs should arrive on the market within a few weeks now, probably aboard the iPhone 12.
The 5nm process, called N5, represents the second generation to take advantage of DUV and EUV (Deep Ultra-Violet and Extreme Ultra-Violet) technologies. The first was the N7 + but it was used on a few occasions. Mass production, we said, has already started for months and the first devices containing chips made with N5 should arrive on the market shortly. Currently the efficiency of the production process is very satisfactory, even better than the predecessors N7 and N10 (with the same time elapsed from the start of mass production). The forecast is that the figure will continue to rise.
The direct evolution of N5 will be N5P, promises a 5% increase in performance and a 10% reduction in energy consumption; next will come N4, which will use more EUV technology but will not require major changes in chip design. The company is pushing to start production in the fourth quarter of 2021, with arrival on the market scheduled for late 2022.
Finally, node N3, at 3 nanometers, which was the highlight of the presentation. TSMC plans to continue using FinFET-structured transistors, a radically different choice from Samsung which will use Gate-all-around (GAA). There are no precise details on how the company will manage to scale the process – it has just mentioned "advanced features". Compared to N5, N3 will deliver 25-30% lower power consumption, 10-15% speed increase, 0.58x area reduction and 1.7x increased density. These are values in line with Samsung's solution – only from the point of view of density is TSMC's process, at least on paper, better. Mass production of the 3 nm chips will begin in the second half of 2022.